Polysilicon has been the gate of choice for MOS transistors for many years. As the gate dielectrics have become thinner and/or of a higher dielectric constant (k), depletion (poly depletion) of carriers in the polysilicon adjacent to the gate dielectric, which has the effect of adding a capacitor in series with the gate dielectric, has become more significant in reducing the overall gate capacitance. A typical effect of poly depletion is to put the equivalent of 6 to 8 Angstroms of silicon oxide in series with the gate dielectric. With gate dielectrics now being able to be made with equivalents of about 10 Angstroms of silicon oxide, the poly depletion is significant to the effective overall gate dielectric thickness as measured electrically. With the improved use of high k dielectrics, the poly depletion will become an even bigger percentage of the overall effective gate dielectric thickness. Further, polysilicon has compatibility issues with many of the high k dielectrics being considered for use.
In the implementation of metal gates, much of the difficulty has been finding metals with work functions that work well for N channel and P channel transistors. Etching these metals is also an issue. Etchants that are selective between the metal and the underlying gate dielectric are useful for this purpose. The integration of the various aspects of choosing the metals for P and N channel devices, the gate dielectric, and the etchants has been difficult to achieve for reliable manufacturing.
Thus there is a need for making a metal gate semiconductor device that improves the integration of various elements used in such a process.